In the part I, we covered some of the key topics of combinational circuit. Logic circuits, Analyze procedure, Design procedure. In this tutorial we will discuss about adders and substractors. Adder is a combinational digital circuit that perform the addition.

## Half-Adder

Half adder is the basic combinational circuit with two inputs and two outputs. It can add two input binary digits and produce sum(S) and carry(C) bits. If inputs are A and B, then sum is the X-OR of the A and B, carry is the AND of the A and B.

**Truth table**

We can simplify and get the Boolean expression using K-Map. (Go to the K-Map)

S = A’B +AB’ = A ⊕ B

C = AB

**Implementation of Half Adder using AND and OR**

**Implementation of Half Adder using AND and X-OR**

But we can also implement half adder using NAND gates. NAND gate is consider as universal Logic gate. Therefore, all logic gates can be implemented with NAND gates.

** Implementation of Half Adder using NAND gates**

## Full-Adder

Full adder is a combinational circuit that perform addition. It adds together two binary digits plus a carry in(C-in) digit and produce two outputs, a sum(S) and a carry out(C-out) bit. Full adders use to get addition of n-bit binary numbers. The addition proceeds on a bit by bit basis, right to left beginning with the least significant bit.

**Truth table**

Simply the Logical expression for C-out in sum using K map.

S = A’B’C_{in} + A’BC’_{in} +AB’C’_{in} +ABC_{in}

C = AB + AC_{in} +BC_{in}

= AB + AC_{in} +BC_{in} (A + A’)

= ABC_{in} + AB + AC_{in} + A’BC_{in}

=AB (1+C_{in}) + AC_{in }+ A’BC_{in}

=AC_{in }+AB + A’BC_{in}

=AB + AC_{in }(B +B’) + A’BC_{in}

= ABC_{in }+ AB + AB’C_{in }+ A’BC_{in}

= AB (C_{in }+ 1) + AB’C_{in }+ A’BC_{in}

= A B’ C_{in} + A B + A’ B C_{in}

=AB + C_{in} (A’B + AB’)

=AB + C_{in} (A ⊕ B)

## Full–Adder Implementation using two Half–Adders

Implement a full adder with two Half adders and one OR gate.

## A 4-bit Binary Adder

Binary adder produces the arithmetic sum of two binary numbers. It is constructed with full adders connected in cascade. The output carry from each full adder is connected to the input carry of the next full adder in chain. Addition of n-bit numbers requires a chain of n full adders or a chain of one-half adder and n-1 full adders.

The design of this circuit by the classical method would require a truth table with 2^{9} =512 entries since there are nine inputs to the circuit. but using an alternative method of cascading a standard function, we obtain a simple and straight forward implementation.

## Carry Propagation

In combinational circuits, the signal must propagate through the gates before the correct output sum is available in the output terminals. Total propagation time is equals to the propagation delay of a typical gate, times the numbers of gate levels in the circuit. The longest propagation delay time in an adder is the time it takes the carry to propagate through the full adder. The last output Sum and Carry will settle to their final correct value only after the carry propagates and ripples through all stages. Carry propagation time is an important attribute of the adder. It limits the speed with which two numbers are added. There are two solutions for reducing carry propagation delay.

- Employ faster gates with reduced delays
- Increase the complexity of the equipment in such a way that the carry delay time is reduced.

## Look-ahead Carry Adder

There are several techniques exist for reducing the carry propagation time in parallel adders. Most widely used technique employs the principle of Carry Look-ahead Logic in most ALU designs. It is faster compared to full adders especially when adding a large number of bits.

The signal from the input carry to output carry propagates through an AND gate and an OR gate, which constitute two gate levels. For an n-bit adder, there are 2n gate levels for the carry to propagate from input to output.

*P _{i} = A_{i} xor B_{i}*

*G _{i} = A_{i} B*

_{i}

Output sum and carry are expressed as follows;

*S _{i} = P_{i }xor C_{i}*

*C _{i+1} = G_{i} + P_{i}C_{i}*

Boolean function for each carry output at each stage

𝐶_{0} = 𝑖𝑛𝑝𝑢𝑡 𝑐𝑎𝑟𝑟𝑦

*C _{1} = G_{0} +P_{0} C_{0}*

*C _{2} = G_{1} +P_{1} C_{1} = G_{1} + P_{1} (G_{0} +P_{0} C_{0}) = G_{1 }+P_{1}G_{0} +P_{1}P_{0}C_{0}*

*C _{2} = G_{2} +P_{2} C_{2} = G_{2 }+P_{2}G_{1} +P_{2}P_{1}G_{0} + P_{2}P_{1}P_{0}C_{0}*

Boolean function for each output carry is expressed in sum of products from. It can be implemented with one level of AND gates followed by an OR gate. Therefore, circuit can add in less time. C_{3} is propagated at the same time as C_{1} and C_{2}. So, all output carries are generated after a delay through two levels of gates. Therefore, all output sums have equal propagation delay times.

## Binary Adder – Subtractor

Binary adder –subtractor is a combinational circuit that capable of both addition and subtraction of binary numbers. The M is the mode control input which is connected to the carry input of the least significant bit of the full adder. The M input decides whether the operation is addition or a subtraction.

There is a xor gate for each Full adder block. One input of xor gate is connected to B while other input is connected to M. When M = 0, the xor gate outputs B. input carry bit (C_{in}) also 0. Hence the circuit is act as Adder.

When the subtraction operation is performed,

M=1, hence the xor gate outputs complement of B. therefore complement of B added to A.

A – B = A + (2’s complement of B)

(2’s complement of B) = (1’s complement of B) + 1

(1’s complement of B) is implemented with inverters. 1 can be added to the sum through an input carry.

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